The present invention relates to techniques for design-specific tuning of computer aided design algorithms, and more specifically, to techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit by comparing the performance of the circuit design in response to different values for selected input parameters and choosing the input parameter values with optimum results on a circuit by circuit basis.
User constraints may include timing and resource usage constraints. Timing constraints, for example, can include the speed of the circuit measured as the maximum frequency of the longest delay path or the worst-case slack. Resource usage constraints include the layout area of a circuit design, use of interconnect or programmable switches, or power consumption.
A compilation tool can implement a circuit design and output data indicating the speed and the resource usage of a circuit design. Quartus II is an example of a prior art circuit compilation tool that is used to program programmable integrated circuits such as a field programmable gate array (FPGAs) or complex programmable logic devices (CPLDs). Quartus II analyzes a user circuit design and outputs data that characterizes the operation of the circuit including the speed and the resource usage of the layout.
FPGAs (such as Altera's Stratix family of products) typically include rows and columns of programmable circuit elements connected by a programmable interconnect network. FPGAs can be instantiated to perform a variety of user functions (designs or circuits).
An example of a programmable circuit element is a logic element, which may contain a look-up table or product-term, possibly a register, and some support circuitry for arithmetic and other special-purpose hardware functions. An FPGA can be configured according to a user circuit design by programming the logic elements, routing resources, and any other programmable circuit elements using technologies such as SRAM, EPROM, FLASH or antifuse cells manufactured on the device for this purpose.
The implementation of a circuit design, often originating with the designer in Verilog, VHDL or schematic, into a physical circuit is typically done with a series of computer-aided design (CAD) tools. This flow is often called compilation. Some elements of this tool flow include synthesis, which converts the behavioral description of a circuit into a netlist of optimized gates targeting the appropriate device, placement and routing (herein called “fitter”) to choose physical locations and wires for implementing the circuit, and timing analysis that computes the expected delay of logic elements and interconnect elements to determine the potential clock-speed or maximum frequency (Fmax) of the circuit.
Some fitter algorithms may begin by placing a user circuit design with a random initial solution. There are numerous random placement solutions, and the choice of starting point can affect the placement quality significantly.
There are numerous input parameter settings in compilation placement and routing that effect output metrics (e.g., speed and resource usage) of a circuit. Similarly, there are numerous opportunities for parameterization in the synthesis portion of the CAD flow; for example, turning on or off various algorithms and techniques, or modifying constant parameters. Many such input parameters or techniques are chosen as defaults in the CAD flow, because they are appropriate for the majority of potential circuits provided to the tool. However, for an individual circuit, it is common that one or more of these techniques will perform better on that circuit with a non-default parameterization.
Therefore, it would be desirable to provide techniques for optimizing numerous parameter settings that effect the placement and synthesis of a user circuit design and specifically on a programmable integrated circuit.